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tny284-290 tinyswitch-4 family www.powerint.com september 2012 energy-effcient, off-line switcher with line compensated overload power ? output power table product 3 230 vac 15% 85-265 vac adapter 1 peak or open frame 2 adapter 1 peak or open frame 2 tny284p/d/k 6 w 11 w 5 w 8.5 w tny285p/d 8.5 w 15 w 6 w 11.5 w tny285k 11 w 15 w 7.5 w 11.5 w tny286p/d 10 w 19 w 7 w 15 w tny286k 13.5 w 19 w 9.5 w 15 w tny287d 11.5 w 23.5 w 7 w 18 w tny287p 13 w 23.5 w 8 w 18 w tny287k 18 w 23.5 w 11 w 16 w tny288p 16 w 28 w 10 w 21.5 w tny288k 23 w 28 w 14.5 w 21.5 w tny289p 18 w 32 w 12 w 25 w tny289k 25 w 32 w 17 w 25 w tny290p 20 w 36.5 w 14 w 28.5 w tny290k 28 w 36.5 w 20 w 28.5 w table 1. output power table. notes: 1. minimum continuous power in a typical non-ventilated enclosed adapter measured at +50 c ambient. use of an external heat sink will increase power capability. 2. minimum peak power capability in any design or minimum continuous power in an open frame design (see key applications considerations). 3. packages: d: so-8c, p: dip-8c, k: esop-12b. see part ordering information. product highlights lowest system cost with enhanced flexibility ? 725 v rated mosfet ? increases bv de-rating margin ? line compensated overload power C no additional components ? dramatically reduces max overload variation over universal input voltage range ? 5% turn on uv threshold: line voltage sense with single external resistor ? simple on/off control, no loop compensation needed ? selectable current limit through bp/m capacitor value ? higher current limit extends peak power or, in open frame applications, maximum continuous power ? lower current limit improves effciency in enclosed adapters/chargers ? allows optimum tinyswitch-4 choice by swapping devices with no other circuit redesign ? tight i 2 f parameter tolerance reduces system cost ? maximizes mosfet and magnetics utilization ? on-time extension C extends low-line regulation range/hold-up time to reduce input bulk capacitance ? self-biased: no bias winding or bias components ? frequency jittering reduces emi flter costs ? pin-out simplifes heat sinking to the pcb ? source pins are electrically quiet for low emii enhanced safety and reliability features ? accurate hysteretic thermal shutdown protection with auto - matic recovery eliminates need for manual reset ? auto-restart delivers <3% of maximum power in short-circuit and open loop fault conditions ? output overvoltage shutdown with optional zener ? fast ac reset with optional uv external resistor ? very low component count enhances reliability and enables single-sided printed circuit board layout ? high bandwidth provides fast turn-on with no overshoot and excellent transient load response ? extended creepage between drain and all other pins improves feld reliability ecosmart ? C extremely energy effcient ? easily meets all global energy effciency regulations ? no-load <30 mw with bias winding, <150 mw at 265 vac without bias winding ? on/off control provides constant effciency down to very light loads C ideal for mandatory cec regulations and eup standby requirements applications ? pc standby and other auxiliary supplies ? dvd/pvr and other low power set top decoders ? supplies for appliances, industrial systems, metering, etc ? chargers/adapters for cell/cordless phones, pdas, digital cameras, mp3/portable audio, shavers, etc. figure 1. typical standby application. pi-6578-101411 wide-range high-voltage dc input d s en/uv bp/m dc output tinyswitch-4 + + figure 2. package options. esop-12b (k package) dip-8c (p package) so-8c (d package)
rev. a 09/12 2 tny284-290 www.powerint.com pin functional description drain (d) pin: this pin is the power mosfet drain connection. it provides internal operating current for both start-up and steady-state operation. bypass/multi-function (bp/m) pin: this pin has multiple functions: ? it is the connection point for an external bypass capacitor for the internally generated 5.85 v supply. ? it is a mode selector for the current limit value, depending on the value of the capacitance added. use of a 0.1 f capaci - tor results in the standard current limit value. use of a 1 f capacitor results in the current limit being reduced to that of the next smaller device size. use of a 10 f capacitor results in the current limit being increased to that of the next larger device size for tny285-290. ? it provides a shutdown function. when the current into the bypass pin exceeds isd, the device latches off until the bp/m voltage drops below 4.9 v, during a power-down or, when the uv function is employed with external resistors connected to the bp/uv pin, by taking the uv/en pin current below i uv minus the reset hysteresis (typ. 18.75 a). this can be used figure 3. functional block diagram. pi-6639-113011 clock oscillator 5.85 v 4.9 v source (s) s r q dc max bypass/ multi-function (bp/m) + - v i limit fault present current limit comparator enable leading edge blanking thermal shutdown + - drain (d) regulator 5.85 v bypass pin under-voltage 1.0 v + v t enable/ under- voltage (en/uv) q 115 a 25 a line under-voltage reset auto- restart counter jitter 1.0 v 6.4 v bypass capacitor select and current limit state machine ovp latch line compensation figure 4. pin confguration. pi-6577-053112 p package (dip-8c) 12 s 11 s 10 s 9 s 8 s 7 s en/uv 1 bp/m 2 n/c 3 n/c 4 d 6 k package (esop-12b) exposed pad (on bottom) internally connected to source pin d package (so-8c) en/uv 1 bp/m 2 d 4 8 s 7 s 6 s 5 s 5 s 7 s 8 s d 4 bp/m 2 en/uv 1 6 s
rev. a 09/12 3 tny284-290 www.powerint.com to provide an output overvoltage function with a zener connected from the bypass/multi-functional pin to a bias winding supply. enable/undervoltage (en/uv) pin: this pin has dual functions: enable input and line undervoltage sense. during normal operation, switching of the power mosfet is controlled by this pin. mosfet switching is terminated when a current greater than a threshold current is drawn from this pin. switching resumes when the current being pulled from the pin drops to less than a threshold current. a modulation of the threshold current reduces group pulsing. the threshold current is between 75 a and 115 a. the enable/undervoltage pin also senses line undervoltage conditions through an external resistor connected to the dc line voltage. if there is no external resistor connected to this pin, tinyswitch-4 detects its absence and disables the line undervoltage function. source (s) pin: this pin is internally connected to the output mosfet source for high-voltage power return and control circuit common. tinyswitch-4 functional description tinyswitch-4 combines a high-voltage power mosfet switch with a power supply controller in one device. unlike conventional pwm (pulse width modulator) controllers, it uses a simple on/off control to regulate the output voltage. the controller consists of an oscillator, enable circuit (sense and logic), current limit state machine, 5.85 v regulator, bypass/ multi-function pin undervoltage, overvoltage circuit, and current limit selection circuitry, over-temperature protection, current limit circuit, leading edge blanking, and a 725 v power mosfet. tinyswitch-4 incorporates additional circuitry for line undervoltage sense, auto-restart, adaptive switching cycle on-time extension, and frequency jitter. figure 3 shows the functional block diagram with the most important features. figure 5. frequency jitter. 600 05 10 136 khz 128 khz v drain ti me (s) pi-2741-041901 500 400 300 200 100 0 oscillator the typical oscillator frequency is internally set to an average of 132 khz. two signals are generated from the oscillator: the maximum duty cycle signal (dc max ) and the clock signal that indicates the beginning of each cycle. the oscillator incorporates circuitry that introduces a small amount of frequency jitter, typically 8 khz peak-to-peak, to minimize emi emission. the modulation rate of the frequency jitter is set to 1 khz to optimize emi reduction for both average and quasi-peak emissions. the frequency jitter should be measured with the oscilloscope triggered at the falling edge of the drain waveform. the waveform in figure 5 illustrates the frequency jitter. enable input and current limit state machine the enable input circuit at the enable/undervoltage pin consists of a low impedance source follower output set at 1.2 v. the current through the source follower is limited to 115 a. when the current out of this pin exceeds the threshold current, a low logic level (disable) is generated at the output of the enable circuit, until the current out of this pin is reduced to less than the threshold current. this enable circuit output is sampled at the beginning of each cycle on the rising edge of the clock signal. if high, the power mosfet is turned on for that cycle (enabled). if low, the power mosfet remains off (disabled). since the sampling is done only at the beginning of each cycle, subsequent changes in the enable/under- voltage pin voltage or current during the remainder of the cycle are ignored. the current limit state machine reduces the current limit by discrete amounts at light loads when tinyswitch-4 is likely to switch in the audible frequency range. the lower current limit raises the effective switching frequency above the audio range and reduces the transformer fux density, including the associated audible noise. the state machine monitors the sequence of enable events to determine the load condition and adjusts the current limit level accordingly in discrete amounts. under most operating conditions (except when close to no-load), the low impedance of the source follower keeps the voltage on the enable/undervoltage pin from going much below 1.2 v in the disabled state. this improves the response time of the optocoupler that is usually connected to this pin. 5.85 v regulator and 6.4 v shunt voltage clamp the 5.85 v regulator charges the bypass capacitor connected to the bypass pin to 5.85 v by drawing a current from the voltage on the drain pin whenever the mosfet is off. the bypass/multi-function pin is the internal supply voltage node. when the mosfet is on, the device operates from the energy stored in the bypass capacitor. extremely low power consumption of the internal circuitry allows tinyswitch-4 to operate continuously from current it takes from the drain pin. a bypass capacitor value of 0.1 f is suffcient for both high frequency decoupling and energy storage. in addition, there is a 6.4 v shunt regulator clamping the bypass/multi-function pin at 6.4 v when current is provided to the bypass/multi-function pin through an
rev. a 09/12 4 tny284-290 www.powerint.com figure 6. auto-restart operation. pi-4098-082305 0 2500 5000 ti me (ms) 0 5 0 10 100 200 300 v drain v dc-output external resistor. this facilitates powering of tinyswitch-4 externally through a bias winding to decrease the no-load consumption to well below 50 mw. bypass/multi-function pin undervoltage the bypass/multi-function pin undervoltage circuitry disables the power mosfet when the bypass/multi- function pin voltage drops below 4.9 v in steady state operation. once the bypass/multi-function pin voltage drops below 4.9 v in steady state operation, it must rise back to 5.85 v to enable (turn-on) the power mosfet. over temperature protection the thermal shutdown circuitry senses the die temperature. the threshold is typically set at 142 c with 75 c hysteresis. when the die temperature rises above this threshold the power mosfet is disabled and remains disabled until the die temperature falls by 75 c, at which point it is re-enabled. a large hysteresis of 75 c (typical) is provided to prevent over- heating of the pc board due to a continuous fault condition. current limit the current limit circuit senses the current in the power mosfet. when this current exceeds the internal threshold (i limit ), the power mosfet is turned off for the remainder of that cycle. the current limit state machine reduces the current limit threshold by discrete amounts under medium and light loads. the leading edge blanking circuit inhibits the current limit comparator for a short time (t leb ) after the power mosfet is turned on. this leading edge blanking time has been set so that current spikes caused by capacitance and secondary-side rectifer reverse recovery time will not cause premature termination of the switching pulse. auto-restart in the event of a fault condition such as output overload, output short-circuit, or an open loop condition, tinyswitch-4 enters into auto-restart operation. an internal counter clocked by the oscillator is reset every time the enable/undervoltage pin is pulled low. if the enable/undervoltage pin is not pulled low for 64 ms, the power mosfet switching is normally disabled for 2.5 seconds (except in the case of line undervoltage condition, in which case it is disabled until the condition is removed). the auto-restart alternately enables and disables the switching of the power mosfet until the fault condition is removed. figure 6 illustrates auto-restart circuit operation in the presence of an output short-circuit. in the event of a line undervoltage condition, the switching of the power mosfet is disabled beyond its normal 2.5 seconds until the line undervoltage condition ends. adaptive switching cycle on-time extension adaptive switching cycle on-time extension keeps the cycle on until current limit is reached, instead of prematurely terminating after the dc max signal goes low. this feature reduces the minimum input voltage required to maintain regulation, extending hold-up time and minimizing the size of bulk capacitor required. the on-time extension is disabled during the start-up of the power supply, until the power supply output reaches regulation. line undervoltage sense circuit the dc line voltage can be monitored by connecting an external resistor from the dc line to the enable/ undervoltage pin. during power-up or when the switching of the power mosfet is disabled in auto-restart, the current into the enable/undervoltage pin must exceed 25 a to initiate switching of the power mosfet. during power-up, this is accomplished by holding the bypass/multi-function pin to 4.9 v while the line undervoltage condition exists. the bypass/multi-function pin then rises from 4.9 v to 5.85 v when the line undervoltage condition goes away. when the switching of the power mosfet is disabled in auto-restart mode and a line undervoltage condition exists, the auto-restart counter is stopped. this stretches the disable time beyond its normal 2.5 seconds until the line undervoltage condition ends. the line undervoltage circuit also detects when there is no external resistor connected to the enable/undervoltage pin (less than ~2 a into the pin). in this case the line undervoltage function is disabled. tinyswitch-4 operation tinyswitch-4 devices operate in the current limit mode. when enabled, the oscillator turns the power mosfet on at the beginning of each cycle. the mosfet is turned off when the current ramps up to the current limit or when the dc max limit is reached. since the highest current limit level and frequency of a tinyswitch-4 design are constant, the power delivered to the load is proportional to the primary inductance of the transformer and peak primary current squared. hence, designing the supply involves calculating the primary inductance of the transformer for the maximum output power required. if the tinyswitch-4 is appropriately chosen for the power level, the current in the calculated inductance will ramp up to current limit before the dc max limit is reached.
rev. a 09/12 5 tny284-290 www.powerint.com v drain v en clock dc drain i max pi-2749-082305 figure 7. operation at near maximum loading. v drain v en clock dc drain i max pi-2667-082305 figure 8. operation at moderately heavy loading. figure 9. operation at medium loading. pi-2377-082305 v drain v en clock dc drain i max pi-2661-082305 v drain v en clock dc drain i max figure 10. operation at very light load. enable function tinyswitch-4 senses the enable/undervoltage pin to determine whether or not to proceed with the next switching cycle. the sequence of cycles is used to determine the current limit. once a cycle is started, it always completes the cycle (even when the enable/undervoltage pin changes state half way through the cycle). this operation results in a power supply in which the output voltage ripple is determined by the output capacitor, amount of energy per switch cycle and the delay of the feedback. the enable/undervoltage pin signal is generated on the secondary by comparing the power supply output voltage with a reference voltage. the enable/undervoltage pin signal is high when the power supply output voltage is less than the reference voltage. in a typical implementation, the enable/ undervoltage pin is driven by an optocoupler. the collector of the optocoupler transistor is connected to the enable/ undervoltage pin and the emitter is connected to the source pin. the optocoupler led is connected in series with
rev. a 09/12 6 tny284-290 www.powerint.com figure 13. normal power-down timing (without uv). figure 14. slow power-down timing with optional external (4 m w ) uv resistor connected to en/uv pin. figure 11. power-up with optional external uv resistor (4 m w ) connected to en/uv pin. figure 12. power-up without optional external uv resistor connected to en/uv pin. pi-2395-030801 0 2.5 5 time (s) 0 100 200 400 300 0 100 200 v dc-input v drain 0 12 t ime (ms) 0 200 400 5 0 10 0 100 200 pi-2383-030801 v dc-input v byp ass v drain pi-2381-1030801 0 12 time (ms) 0 200 400 5 0 10 0 100 200 v dc-input v byp ass v drain pi-2348-030801 0 .5 1 time (s) 0 100 200 300 0 100 200 400 v dc-input v drain a zener diode across the dc output voltage to be regulated. when the output voltage exceeds the target regulation voltage level (optocoupler led voltage drop plus zener voltage), the optocoupler led will start to conduct, pulling the enable/ undervoltage pin low. the zener diode can be replaced by a tl431 reference circuit for improved accuracy. on/off operation with current limit state machine the internal clock of the tinyswitch-4 runs all the time. at the beginning of each clock cycle, it samples the enable/ undervoltage pin to decide whether or not to implement a switch cycle, and based on the sequence of samples over multiple cycles, it determines the appropriate current limit. at high loads, the state machine sets the current limit to its highest value. at lighter loads, the state machine sets the current limit to reduced values. at near maximum load, tinyswitch-4 will conduct during nearly all of its clock cycles (figure 7). at slightly lower load, it will skip additional cycles in order to maintain voltage regulation at the power supply output (figure 8). at medium loads, cycles will be skipped and the current limit will be reduced (figure 9). at very light loads, the current limit will be reduced even further (figure 10). only a small percentage of cycles will occur to satisfy the power consumption of the power supply. the response time of the on/off control scheme is very fast compared to pwm control. this provides tight regulation and excellent transient response. power-up/down the tinyswitch-4 requires only a 0.1 f capacitor on the bypass/multi-function pin to operate with standard
rev. a 09/12 7 tny284-290 www.powerint.com current limit. because of its small size, the time to charge this capacitor is kept to an absolute minimum, typically 0.6 ms. the time to charge will vary in proportion to the bypass/multi- function pin capacitor value when selecting different current limits. due to the high bandwidth of the on/off feedback, there is no overshoot at the power supply output. when an external resistor (4 m w ) is connected from the positive dc input to the enable/undervoltage pin, the power mosfet switching will be delayed during power-up until the dc line voltage exceeds the threshold (100 v). figures 11 and 12 show the power-up timing waveform in applications with and without an external resistor (4 m w ) connected to the enable/ undervoltage pin. under start-up and overload conditions, when the conduction time is less than 400 ns, the device reduces the switching frequency to maintain control of the peak drain current. during power-down, when an external resistor is used, the power mosfet will switch for 64 ms after the output loses regulation. the power mosfet will then remain off without any glitches since the undervoltage function prohibits restart when the line voltage is low. figure 13 illustrates a typical power-down timing waveform. figure 14 illustrates a very slow power-down timing waveform as in standby applications. the external resistor (4 m w ) is connected to the enable/undervoltage pin in this case to prevent unwanted restarts. no bias winding is needed to provide power to the chip because it draws the power directly from the drain pin (see functional description). this has two main benefts. first, for a nominal application, this eliminates the cost of a bias winding and associated components. secondly, for battery charger applications, the current-voltage characteristic often allows the output voltage to fall close to 0 v while still delivering power. tinyswitch-4 accomplishes this without a forward bias winding and its many associated components. for applications that require very low no-load power consumption (50 mw), a resistor from a bias winding to the bypass/multi-function pin can provide the power to the chip. the minimum recommended current supplied is 1 ma. the bypass/multi-function pin in this case will be clamped at 6.4 v. this method will eliminate the power draw from the drain pin, thereby reducing the no-load power consumption and improving full-load effciency. current limit operation each switching cycle is terminated when the drain current reaches the current limit of the device. current limit operation provides good line ripple rejection and relatively constant power delivery independent of input voltage. bypass/multi-function pin capacitor the bypass/multi-function pin can use a ceramic capacitor as small as 0.1 f for decoupling the internal power supply of the device. a larger capacitor size can be used to adjust the current limit. for tny285-290, a 1 f bypass/ multi-functional pin capacitor will select a lower current limit equal to the standard current limit of the next smaller device and a 10 f bypass/multi-functional pin capacitor will select a higher current limit equal to the standard current limit of the next larger device. the higher current limit level of the tny290 is set to 850 ma typical. the tny284 mosfet does not have the capability for increased current limit so this feature is not available in this device. 85 115 100 130 145 160 175 190 250 265 220 205 235 input voltage (vac) maximum over power (w) 40 35 30 25 20 tny290 tny280 pi-6788-052312 figure 15. comparison of maximum overpower for tinyswitch-4 and tinyswitch-iii as a function of input voltage (data collected from rdk-295 20 w reference design).
rev. a 09/12 8 tny284-290 www.powerint.com applications example the circuit shown in figure 16 is a low cost, high effciency, fyback power supply designed for 5 v, 4 a output from universal input using the tny290pg. the supply features undervoltage lockout, primary sensed output overvoltage latching shutdown protection, high effciency (>80%), and very low no-load consumption (<50 mw at 265 vac). output regulation is accomplished using a simple zener reference and optocoupler feedback. the rectifed and fltered input voltage is applied to the primary winding of t1. the other side of the transformer primary is driven by the integrated mosfet in u1. diode d1, c3, r1, and vr1 comprise the clamp circuit, limiting the leakage inductance turn-off voltage spike on the drain pin to a safe value. the output voltage is regulated by tl431 u2. when the output voltage ripple exceeds the sum of the u2 (cathode d6) and optocoupler led forward drop, current will fow in the optocoupler led. this will cause the transistor of the optocoupler to sink current. when this current exceeds the enable pin threshold current the next switching cycle is inhibited. when the output voltage falls below the feedback threshold, a conduction cycle is allowed to occur and, by adjusting the number of enabled cycles, output regulation is maintained. as the load reduces, the number of enabled cycles decreases, lowering the effective switching frequency and scaling switching losses with load. this provides almost constant effciency down to very light loads, ideal for meeting energy effciency requirements. as the tinyswitch-4 devices are completely self-powered, there is no requirement for an auxiliary or bias winding on the transformer. however by adding a bias winding, the output overvoltage protection feature can be confgured, protecting the load against open feedback loop faults. when an overvoltage condition occurs, such that bias voltage exceeds the sum of vr2 and the bypass/multifunction (bypass/multi-functional) pin voltage, current begins to fow into the bypass/multi-functional pin. when this current exceeds i sd the internal latching shutdown circuit in tinyswitch-4 is activated. this condition is reset when the enable/undervoltage pin current fowing through r12 and r13 drop below 18.75 a each ac line half-cycle. the confguration of figure 16 is therefore non-latching for an overvoltage fault. latching overvoltage protection can be achieved by connecting r12 and r13 to the positive terminal of c2, at the expense of higher standby consumption. in the example shown, on opening the loop, the ovp trips at an output of 17 v. for lower no-load input power consumption, the bias winding may also be used to supply the tinyswitch-4 device. resistor figure 16. tny290pg, 5 v, 4 a universal input power supply. d s en/uv bp/m 90 - 295 vac 5 v, 4 a rtn pi-6559-062012 r12 2 m ? r13 2 m ? r15 1.5 m ? 1/8 w c9 10 f 16 v c11 2.2 f 50 v r14 3.3 k ? 1/8 w r8 1 k ? 1/8 w r7 10 k ? 1% r2 8.2 ? r3 4.7 ? 1/2 w r9 47 ? r4 30 k ? 1/8 w r6 10 k ? 1% r1 22 ? 1/2 w d1 uf4006-e3 d3 1n4937 u2 tl431 vr2 1n5254 27 v vr1 p6ke150a tinyswitch-4 u1 tny290pg u3 pc817 in a pc standby application input stage will be part of main power supply input d4 stps30l60ct rt1 6 ? f1 5 a c3 2.2 nf 1 kv br1 2kbp10m 1000 v c2 68 f 450 v c4 100 f 50 v c8 1000 f 10 v l1 10 mh l2 2.2 h c5 1.5 nf 100 v c6, c7 1500 f 10 v c10 47 nf 100 v c13 2.2 nf 250 vac 1 9,10 7,8 t1 ee22 4 5 3 c1 100 nf 275 vac c16 100 nf 100 v
rev. a 09/12 9 tny284-290 www.powerint.com r4 feeds current into the bypass/multi-functional pin, inhibiting the internal high-voltage current source that normally maintains the bypass/multi-functional pin capacitor voltage (c7) during the internal mosfet off-time. this reduces the no-load consumption of this design from 140 mw to 40 mw at 265 vac. undervoltage lockout is confgured by r5 connected between the dc bus and enable/undervoltage pin of u1. when present, switching is inhibited until the current in the enable/ undervoltage pin exceeds 25 a. this allows the start-up voltage to be programmed within the normal operating input voltage range, preventing glitching of the output under abnormal low voltage conditions and also on removal of the ac input. in addition to the simple input pi flter (c1, l1, c2) for differential mode emi, this design makes use of e-shield? shielding techniques in the transformer to reduce common mode emi displacement currents, and r2 and c4 as a damping network to reduce high frequency transformer ringing. these techniques, combined with the frequency jitter of tny288, give excellent conducted and radiated emi performance with this design achieving >12 db v of margin to en55022 class b conducted emi limits. for design fexibility the value of c7 can be selected to pick one of the 3 current limits options in u1. this allows the designer to select the current limit appropriate for the application. ? standard current limit (i limit ) is selected with a 0.1 f bypass/ multi-functional pin capacitor and is the normal choice for typical enclosed adapter applications. ? when a 1 f bypass/multi-functional pin capacitor is used, the current limit is reduced (i limitred or i limit -1) offering reduced rms device currents and therefore improved effciency, but at the expense of maximum power capability. this is ideal for thermally challenging designs where dissipa - tion must be minimized. ? when a 10 f bypass/multi-functional pin capacitor is used, the current limit is increased (i limitinc or i limit +1), extending the power capability for applications requiring higher peak power or continuous power where the thermal conditions allow. further fexibility comes from the current limits between adjacent tinyswitch-4 family members being compatible. the reduced current limit of a given device is equal to the standard current limit of the next smaller device and the increased current limit is equal to the standard current limit of the next larger device. key application considerations tinyswitch-4 vs. tinyswitch-iii table 2 compares the features and performance differences between tinyswitch-4 and tinyswitch-iii. tinyswitch-4 is pin compatible to tinyswitch-iii with improved features. it requires minimum design effort to adapt into a new design. in addition to the feature enhancement, tinyswitch-4 offers two new packages; esop-12b (k) and so-8c (d) to meet various application requirements. tinyswitch-4 design considerations output power table the data sheet output power table (table 1) represents the minimum practical continuous output power level that can be obtained under the following assumed conditions: 1. the minimum dc input voltage is 100 v or higher for 85 vac input, or 220 v or higher for 230 vac input or 115 vac with a voltage doubler. the value of the input capacitance should be sized to meet these criteria for ac input designs. 2. effciency of 75%. 3. minimum data sheet value of i 2 f. 4. transformer primary inductance tolerance of 10%. 5. refected output voltage (v or ) of 135 v. 6. voltage only output of 12 v with a fast pn rectifer diode. 7. continuous conduction mode operation with transient k p * value of 0.25. 8. increased current limit is selected for peak and open frame power columns and standard current limit for adapter columns. 9. the part is board mounted with source pins soldered to a suffcient area of copper and/or a heat sink is used to keep the source pin temperature at or below 110 c. 10. ambient temperature of 50 c for open frame designs and 40 c for sealed adapters. *below a value of 1, k p is the ratio of ripple to peak primary current. to prevent reduced power capability due to premature termination of switching cycles a transient k p limit of 0.25 is recommended. this prevents the initial current limit (i init ) from being exceeded at mosfet turn-on. for reference, table 3 provides the minimum practical power delivered from each family member at the three selectable current limit values. this assumes open frame operation (not thermally limited) and otherwise the same conditions as listed above. these numbers are useful to identify the correct current limit to select for a given device and output power requirement. overvoltage protection the output overvoltage protection provided by tinyswitch-4 uses an internal latch that is triggered by a threshold current of approximately 5.5 ma into the bypass/multi-functional pin. in addition to an internal flter, the bypass/multi- functional pin capacitor forms an external flter providing noise immunity from inadvertent triggering. for the bypass table 2. comparisons between tinyswitch-iii and tinyswitch-4. function tinyswitch-iii tinyswitch-4 bv dss 700 v 725 v line compensated ocp n/a yes typical ocp change from 85 vac to 265 vac >40% <15% uv threshold 25 a 10% 25 a 5% v bp reset voltage 2.6 v typical 3.0 v typical packages dip-8c (p), smd-8c (g) dip-8c (p), esop-12b (k ), so-8c (d)
rev. a 09/12 10 tny284-290 www.powerint.com capacitor to be effective as a high frequency flter, the capacitor should be located as close as possible to the source and bypass/multi-functional pins of the device. for best performance of the ovp function, it is recommended that a relatively high bias winding voltage is used, in the range of 15 v - 30 v. this minimizes the error voltage on the bias winding due to leakage inductance and also ensures adequate voltage during no-load operation from which to supply the bypass/multi-functional pin for reduced no-load consumption. selecting the zener diode voltage to be approximately 6 v above the bias winding voltage (28 v for 22 v bias winding) gives good ovp performance for most designs, but can be adjusted to compensate for variations in leakage inductance. adding additional fltering can be achieved by inserting a low value (10 w to 47 w ) resistor in series with the bias winding diode and/or the ovp zener as shown by r7 and r3 in figure 16. the resistor in series with the ovp zener also limits the maximum current into the bypass/multi-functional pin. reducing no-load consumption as tinyswitch-4 is self-powered from the bypass/multi- functional pin capacitor, there is no need for an auxiliary or bias winding to be provided on the transformer for this purpose. typical no-load consumption when self-powered is <150 mw at 265 vac input. the addition of a bias winding can reduce this down to <50 mw by supplying the tinyswitch-4 from the lower bias voltage and inhibiting the internal high-voltage current source. to achieve this, select the value of the resistor (r8 in figure 16) to provide the data sheet drain supply current. in practice, due to the reduction of the bias voltage at low load, start with a value equal to 40% greater than the data sheet maximum current, and then increase the value of the resistor to give the lowest no-load consumption. audible noise the cycle skipping mode of operation used in tinyswitch-4 can generate audio frequency components in the transformer. to limit this audible noise generation the transformer should be designed such that the peak core fux density is below 3000 gauss (300 mt). following this guideline and using the standard transformer production technique of dip varnishing practically eliminates audible noise. vacuum impregnation of the transformer should not be used due to the high primary capacitance and increased losses that result. higher fux densities are possible, however careful evaluation of the audible noise performance should be made using production transformer samples before approving the design. ceramic capacitors that use dielectrics such as z5u, when used in clamp circuits, may also generate audio noise. if this is the case, try replacing them with a capacitor having a different dielectric or construction, for example a flm type. tinyswitch-4 layout considerations layout see figure 17 for a recommended circuit board layout for tinyswitch-4. single point grounding use a single point ground connection from the input flter capacitor to the area of copper connected to the source pins. bypass capacitor (c bp ) the bypass/multi-functional pin capacitor must be located directly adjacent to the bypass/multi-functional and source pins. if a 0.1 f bypass capacitor has been selected it should be a high frequency ceramic type (e.g. with x7r dielectric). it must be placed directly between the enable and source pins to flter external noise entering the bypass pin. if a 1 f or 10 f bypass capacitor was selected then an additional 0.1 f capacitor should be added across bypass and source pins to provide noise fltering (see figure 17). enable/undervoltage pin keep traces connected to the enable/undervoltage pin short and, as far as is practical, away from all other traces and nodes above source potential including, but not limited to, the bypass, drain and bias supply diode anode nodes. primary loop area the area of the primary loop that connects the input flter capacitor, transformer primary and tinyswitch-4 should be kept as small as possible. primary clamp circuit a clamp is used to limit peak voltage on the drain pin at turn-off. this can be achieved by using an rcd clamp or a zener (~200 v) and diode clamp across the primary winding. to reduce emi, minimize the loop from the clamp components to the transformer and tinyswitch-4. thermal considerations the source pins are internally connected to the ic lead frame and provide the main path to remove heat from the device. therefore all the source pins should be connected to a copper area underneath the tinyswitch-4 to act not only as a single point ground, but also as a heat sink. as this area is connected to the quiet source node, this area should be maximized for good heat sinking. similarly for axial output diodes, maximize the pcb area connected to the cathode. peak output power table product 230 vac 15% 85-265 vac i limit -1 i limit i limit +1 i limit -1 i limit i limit +1 tny284p 9.1 w 10.9 w 9.1 w 7.1 w 8.5 w 7.1 w tny285p 10.8 w 12 w 15.1 w 8.4 w 9.3 w 11.8 w tny286p 11.8 w 15.3 w 19.4 w 9.2 w 11.9 w 15.1 w tny287p 15.1 w 19.6 w 23.7 w 11.8 w 15.3 w 18.5 w tny288p 19.4 w 24 w 28 w 15.1 w 18.6 w 21.8 w tny289p 23.7 w 28.4 w 32.2 w 18.5 w 22 w 25.2 w tny290p 28 w 32.7 w 36.6 w 21.8 w 25.4 w 28.5 w table 3. minimum practical power at three selectable current limit levels.
rev. a 09/12 11 tny284-290 www.powerint.com y capacitor the placement of the y capacitor should be directly from the primary input flter capacitor positive terminal to the common/ return terminal of the transformer secondary. such a placement will route high magnitude common mode surge currents away from the tinyswitch-4 device. note C if an input (c, l, c) emi flter is used then the inductor in the flter should be placed between the negative terminals of the input flter capacitors. optocoupler place the optocoupler physically close to the tinyswitch-4 to minimizing the primary-side trace lengths. keep the high current, high-voltage drain and clamp traces away from the optocoupler to prevent noise pick up. output diode for best performance, the area of the loop connecting the secondary winding, the output diode and the output flter capacitor, should be minimized. in addition, suffcient copper area should be provided at the anode and cathode terminals of the diode for heat sinking. a larger area is preferred at the quiet cathode terminal. a large anode area can increase high frequency radiated emi. pc board leakage currents tinyswitch-4 is designed to optimize energy effciency across the power range and particularly in standby/no-load conditions. current consumption has therefore been minimized to achieve this performance. the enable/undervoltage pin under- voltage feature for example has a low threshold (~1 a) to detect whether an undervoltage resistor is present. figure 17. recommended circuit board layout for tinyswitch-4 with undervoltage lock out resistor. parasitic leakage currents into the enable/undervoltage pin are normally well below this 1 a threshold when pc board assembly is in a well controlled production facility. however, high humidity conditions together with board and/or package contamination, either from no-clean fux or other contaminants, can reduce the surface resistivity enough to allow parasitic currents >1 a to fow into the enable/undervoltage pin. these currents can fow from higher voltage exposed solder pads close to the enable/undervoltage pin such as the bypass/multi-functional pin solder pad preventing the design from starting up. designs that make use of the undervoltage lockout feature by connecting a resistor from the high-voltage rail to the enable/undervoltage pin are not affected. if the contamination levels in the pc board assembly facility are unknown, the application is open frame or operates in a high pollution degree environment and the design does not make use of the undervoltage lockout feature, then an optional 390 k w resistor should be added from enable/undervoltage pin to source pin to ensure that the parasitic leakage current into the enable/undervoltage pin is well below 1 a. note that typical values for surface insulation resistance (sir) where no-clean fux has been applied according to the suppliers guidelines are >>10 m w and do not cause this issue. top view pi-6651-060612 opto- coupler + - high-voltage + - dc out input filter capacitor *c hf /c bp output rectier c bp safety spacing t r a n s f o r m e r pri sec bias d output filter capacitor *c hf is a 0.1 f high frequency noise bypass capacitor (the high frequency 0.1 f capacitor eliminates need for c bp if i limit selection requires 0.1 f). maximize hatched copper areas ( ) for optimum heat sinking bp/m en/ uv y1- capacitor s s s s pri bias tinyswitch-4
rev. a 09/12 12 tny284-290 www.powerint.com quick design checklist as with any power supply design, all tinyswitch-4 designs should be verifed on the bench to make sure that component specifcations are not exceeded under worst case conditions. the following minimum set of tests is strongly recommended: 1. maximum drain voltage C verify that v ds does not exceed 675 v at highest input voltage and peak (overload) output power. the 50 v margin to the 725 v bv dss specifcation gives margin for design variation. 2. maximum drain current C at maximum ambient temperature, maximum input voltage and peak output (overload) power, verify drain current waveforms for any signs of transformer saturation and excessive leading edge current spikes at start-up. repeat under steady-state conditions and verify that the leading edge current spike event is below i limit(min) at the end of the t leb(min) . under all conditions, the maximum drain current should be below the specifed absolute maximum ratings. 3. thermal check C at specifed maximum output power, minimum input voltage and maximum ambient temperature, verify that the temperature specifcations are not exceeded for tinyswitch-4, transformer, output diode, and output capacitors. enough thermal margin should be allowed for part-to-part variation of the r ds(on) of tinyswitch-4 as specifed in the data sheet. under low-line, maximum power, a maximum tinyswitch-4 source pin temperature of 110 c is recommended to allow for these variations.
rev. a 09/12 13 tny284-290 www.powerint.com absolute maximum ratings (1,4) drain voltage ................................................... -0.3 v to 725 v drain peak current: tny284 ......................... 400 (750) ma (2) tny285 ....................... 560 (1050) ma (2) tny286 ....................... 720 (1350) ma (2) tny287 ....................... 880 (1650) ma (2) tny288 ..................... 1040 (1950) ma (2) tny289 ..................... 1200 (2250) ma (2) tny290 ..................... 1360 (2550) ma (2) en/uv voltage ...................................................... -0.3 v to 9 v en/uv current ........................................................... ... 100 ma bp/m voltage .................................................. ...... -0.3 v to 9 v storage temperature ...................................... -65 c to 150 c maximum junction temperature (3) ................... -40 c to 150 c lead temperature (4) ......................................................... 260 c notes: 1. all voltages referenced to source, ta = 25 c. 2. the higher peak drain current is allowed while the drain voltage is simultaneously less than 400 v. 3. normally limited by internal circuitry. 4. 1/16 in. from case for 5 seconds. 5. maximum ratings specifed may be applied one at a time, without causing permanent damage to the product. exposure to absolute rating conditions for extended periods of time may affect product reliability. thermal resistance thermal impedance: p package: ( q ja ) ............................ .... 70 c/w (2) ; 60 c/w (3) ( q jc ) (1) .................................................. 11 c/w d package: ( q ja ) ............................ .. 100 c/w (2) ; 80 c/w (3) ( q jc ) (1) .................................................. 30 c/w k package: ( q ja ) ............................ .... 45 c/w (2) ; 38 c/w (3) ( q jc ) (4) .................................................... 2 c/w notes: 1. measured on the source pin close to the plastic interface. 2. soldered to 0.36 sq. in. (232 mm 2 ), 2 oz. (610 g/m 2 ) copper clad. 3. soldered to 1 sq. in. (645 mm 2 ), 2 oz. (610 g/m 2 ) copper clad. 4. the case temperature is measured at the bottom-side exposed pad. parameter symbol conditions source = 0 v; t j = -40 to 125 c see figure 18 (unless otherwise specifed) min typ max units control functions output frequency in standard mode f osc t j = 25 c see figure 5 average 124 132 140 khz peak-to-peak jitter 8 maximum duty cycle dc max s1 open 62 67 % en/uv pin upper turnoff threshold current i dis -150 -122 -90 a en/uv pin voltage v en i en/uv = 25 a 1.8 2.2 2.6 v i en/uv = -25 a 0.8 1.2 1.6 drain supply current i s1 en/uv current > i dis (mosfet not switching) see note a 330 a i s2 en/uv open (mosfet switching at f osc ) see note b tny284 360 400 a tny285 410 440 tny286 430 470 tny287 510 550 tny288 615 650 tny289 715 800 tny290 875 930
rev. a 09/12 14 tny284-290 www.powerint.com parameter symbol conditions source = 0 v; t j = -40 to 125 c see figure 18 (unless otherwise specifed) min typ max units control functions (cont.) bp/m pin charge current i ch1 v bp/m = 0 v, t j = 25 c see note c, d -6.5 -4.5 -2.5 ma i ch2 v bp/m = 4 v, t j = 25 c see note c, d -4.7 -2.8 -1.4 bp/m pin voltage v bp/m see note c 5.6 5.85 6.3 v bp/m pin voltage hysteresis v bp/mh 0.80 0.95 1.20 v bp/m pin shunt voltage v shunt i bp = 2 ma 6.0 6.4 6.85 v en/uv pin line under- voltage threshold i luv t j = 25 c 23.75 25 26.25 a en/uv pin C reset hysteresis (following latch off with bp/m pin current >i sd ) t j = 25 c see note g 3 5 8 a circuit protection standard current limit (bp/m capacitor = 0.1 f) see note d i limit di/dt = 50 ma/ s t j = 25 c see note e tny284p/d/k 233 250 267 ma di/dt = 55 ma/ s t j = 25 c see note e tny285p/d/k 256 275 294 di/dt = 70 ma/ s t j = 25 c see note e tny286p/d/k 326 350 374 di/dt = 90 ma/ s t j = 25 c see note e tny287p/d/k 419 450 481 di/dt = 110 ma/ s t j = 25 c see note e tny288p/k 512 550 588 di/dt = 130 ma/ s t j = 25 c see note e tny289p/k 605 650 695 di/dt = 150 ma/ s t j = 25 c see note e tny290p/k 698 750 802
rev. a 09/12 15 tny284-290 www.powerint.com parameter symbol conditions source = 0 v; t j = -40 to 125 c see figure 18 (unless otherwise specifed) min typ max units circuit protection (cont.) reduced current limit (bp/m capacitor = 1 f) see note d i limitred di/dt = 42 ma/ s t j = 25 c see note e tny284p/d/k 196 210 233 ma di/dt = 50 ma/ s t j = 25 c see note e tny285p/d/k 233 250 277 di/dt = 55 ma/ s t j = 25 c see notes e tny286p/d/k 256 275 305 di/dt = 70 ma/ s t j = 25 c see notes e tny287p/d/k 326 350 388 di/dt = 90 ma/ s t j = 25 c see notes e tny288p/k 419 450 499 di/dt = 110 ma/ s t j = 25 c see notes e tny289p/k 512 550 610 di/dt = 130 ma/ s t j = 25 c see notes e tny290p/k 605 650 721 increased current limit (bp/m capacitor = 10 f) see note d i limitinc di/dt = 42 ma/ s t j = 25 c see notes e, f tny284p/d/k 196 210 233 ma di/dt = 70 ma/ s t j = 25 c see notes e tny285p/d/k 326 350 388 di/dt = 90 ma/ s t j = 25 c see notes e tny286p/d/k 419 450 499 di/dt = 110 ma/ s t j = 25 c see notes e tny287p/d/k 512 550 610 di/dt = 130 ma/ s t j = 25 c see notes e tny288p/k 605 650 721 di/dt = 150 ma/ s t j = 25 c see notes e tny289p/k 698 750 833 di/dt = 170 ma/ s t j = 25 c see notes e tny290p/k 791 850 943
rev. a 09/12 16 tny284-290 www.powerint.com parameter symbol conditions source = 0 v; t j = -40 to 125 c see figure 18 (unless otherwise specifed) min typ max units circuit protection (cont.) power coeffcient i 2 f standard current limit, i 2 f = i limit(typ) 2 f osc(typ) t j = 25 c tny284-290 0.9 i 2 f i 2 f 1.12 i 2 f a 2 hz reduced current limit, i 2 f = i limitred(typ) 2 f osc(typ) t j = 25 c tny284-290 0.9 i 2 f i 2 f 1.16 i 2 f increased current limit, i 2 f = i limitinc(typ) 2 f osc(typ) t j = 25 c tny284-290 0.9 i 2 f i 2 f 1.16 i 2 f initial current limit i init see figure 20 t j = 25 c, see note g 0.75 i limit(min) ma leading edge blanking time t leb t j = 25 c see note g 170 215 ns current limit delay t ild t j = 25 c see note g, h 150 ns thermal shutdown temperature t sd 135 142 150 c thermal shutdown hysteresis t sdh 75 c bp/m pin shutdown threshold current i sd 4 6.5 9 ma bp/m pin power-up reset threshold voltage v bp/m(reset) 1.6 3.0 3.6 v output on-state resistance r ds(on) tny284 i d = 25 ma t j = 25 c 28 32 w t j = 100 c 42 48 tny285 i d = 28 ma t j = 25 c 19 22 t j = 100 c 29 33 tny286 i d = 35 ma t j = 25 c 14 16 t j = 100 c 21 24
rev. a 09/12 17 tny284-290 www.powerint.com parameter symbol conditions source = 0 v; t j = -40 to 125 c see figure 18 (unless otherwise specifed) min typ max units output (cont.) on-state resistance r ds(on) tny287 i d = 45 ma t j = 25 c 7.8 9.0 w t j = 100 c 11.7 13.5 tny288 i d = 55 ma t j = 25 c 5.2 6.0 t j = 100 c 7.8 9.0 tny289 i d = 65 ma t j = 25 c 3.9 4.5 t j = 100 c 5.8 6.7 tny290 i d = 75 ma t j = 25 c 2.6 3.0 t j = 100 c 3.9 4.5 off-state drain leakage current i dss1 v bp/m = 6.2 v v en/uv = 0 v v ds = 560 v t j = 125 c see note i tny284-286 50 a tny287-288 100 tny289-290 200 i dss2 v bp/m = 6.2 v v en/uv = 0 v v ds = 375 v, t j = 50 c see note g, i 15 breakdown voltage bv dss v bp = 6.2 v, v en/uv = 0 v, see note j, t j = 25 c 725 v drain supply voltage 50 v auto-restart on-time at f osc t ar t j = 25 c see note k 64 ms auto-restart duty cycle dc ar t j = 25 c 3 %
rev. a 09/12 18 tny284-290 www.powerint.com notes: a. i s1 is an accurate estimate of device controller current consumption at no-load, since operating frequency is so low under these conditions. total device consumption at no-load is the sum of i s1 and i dss2 . b. since the output mosfet is switching, it is diffcult to isolate the switching current from the supply current at the drain. an alternative is to measure the bypass/multi-functional pin current at 6.1 v. c. bypass/multi-functional pin is not intended for sourcing supply current to external circuitry. d. to ensure correct current limit it is recommended that nominal 0.1 f / 1 f / 10 f capacitors are used. in addition, the bp/m capacitor value tolerance should be equal or better than indicated below across the ambient temperature range of the target application. the minimum and maximum capacitor values are guaranteed by characterization. e. for current limit at other di/dt values, refer to figure 25. f. tny284 does not have an increased current limit value, but with a 10 f bypass/multi-functional pin capacitor the current limit is the same as with a 1 f bypass/multi-functional pin capacitor (reduced current limit value). g. this parameter is derived from characterization. h. this parameter is derived from the change in current limit measured at 1x and 4x of the di/dt shown in the i limit specifcation. i. i dss1 is the worst case off state leakage specifcation at 80% of bv dss and maximum operating junction temperature. i dss2 is a typical specifcation under worst case application conditions (rectifed 265 vac) for no-load consumption calculations. j. breakdown voltage may be checked against minimum bv dss specifcation by ramping the drain pin voltage up to but not exceeding minimum bv dss . k. auto-restart on time has the same temperature characteristics as the oscillator (inversely proportional to frequency). nominal bp/m pin cap value tolerance relative to nominal capacitor value min max 0.1 f -60% +100% 1 f -50% +100% 10 f -50% na
rev. a 09/12 19 tny284-290 www.powerint.com pi-4079-080905 0.1 f 10 v 50 v 470 5 s2 470 note: this test cir cuit is not applicable for curr ent limit or output characteristic measur ements. sd en/uv s s bp/m s 150 v s1 2 m pi-2364-012699 en/uv t p t en/uv dc max t p = 1 f osc v drain (internal signal) figure 18. general test circuit. figure 19. duty cycle measurement. figure 20. output enable timing. t on (s) current limit (normalized ) 1.10 1.00 0.95 1.05 0.90 0.85 0.80 0.75 0.70 0.65 0.60 0 1 2 3 4 5 6 pi-6803-060512 typical minimum maximum t j = 25 c figure 21. current limit vs. t on for tny284~287. figure 22. current limit vs. t on for tny288~290. t on (s) current limit (normalized ) 1.10 1.00 0.95 1.05 0.90 0.85 0.80 0.75 0.70 0.65 0.60 0 1 2 3 4 5 6 pi-6804-060112 typical minimum maximum t j = 25 c typical performance characteristics
rev. a 09/12 20 tny284-290 www.powerint.com figure 24. standard current limit vs. temperature. figure 26. output characteristic. figure 27. c oss vs. drain voltage. figure 25. standard current limit vs. di/dt. figure 28. drain capacitance power. drain voltage (v) drain capacitance (pf) pi-6771-051112 0 100 200 300 400 500 600 1 10 100 1000 tny284 1.0 tny285 1.5 tny286 2.0 tny287 3.5 tny288 5.6 tny289 7.9 tny290 11.2 scaling factors: drain voltage (v) power (mw) pi-6772-051112 0 100 200 300 400 500 600 0 10 20 30 40 tny284 1.0 tny285 1.5 tny286 2.0 tny287 3.5 tny288 5.6 tny289 7.9 tny290 11.2 scaling factors: 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 1 2 3 4 normalized di/dt pi-6785-052412 normalized current limit (see figure 21) tny284 50 ma/s tny285 55 ma/s tny286 70 ma/s tny287 90 ma/s tny288 110 ma/s tny289 130 ma/s tny290 150 ma/s normalized di/dt = 1 note: for the normalized current limit value, use the typical current limit specied for the appropriate bp/m capacitor. drain voltage (v) drain current (ma) 300 250 200 100 50 150 0 0 2 4 6 8 10 t case =25 c t case =100 c pi-6786-052412 tny284 1.0 tny285 1.5 tny286 2.0 tny287 3.5 tny288 5.6 tny289 7.9 tny290 11.2 scaling factors: temperature (c) standard current limit (normalized to 25 c) 1.05 1.00 95 90 85 80 -40 0 -20 20 40 60 80 100 120 pi-6787-053112 figure 23. breakdown vs. temperature. 1.1 1.0 0.9 -50 -25 02 55 07 5 100 125 150 junction temperature (c) breakdown voltage (normalized to 25 c) pi-2213-012301 typical performance characteristics (cont.)
rev. a 09/12 21 tny284-290 www.powerint.com 1.2 1.0 0.8 0.6 0.4 0.2 0 -50 -25 02 55 07 5 100 125 junction t emperature (c) pi-4281-012306 under-v oltage threshold (normalized to 25 c) figure 29. undervoltage threshold vs. temperarture. typical performance characteristics (cont.)
rev. a 09/12 22 tny284-290 www.powerint.com notes: 1. package dimensions conform to jedec specification ms-001-ab (issue b 7/85) for standard dual-in-line (dip) package with .300 inch row spacing. 2. controlling dimensions are inches. millimeter sizes are shown in parentheses. 3. dimensions shown do not include mold flash or other protrusions. mold flash or protrusions shall not exceed .006 (.15) on any side. 4. pin locations start with pin 1, and continue counter-clock- wise to pin 8 when viewed from the top. the notch and/or dimple are aids in locating pin 1. pin 3 is omitted. 5. minimum metal to metal spacing at the package body for the omitted lead location is .137 inch (3.48 mm). 6. lead width measured at package body . 7. lead spacing measured with the leads constrained to be perpendicular to plane t. .008 (.20) .015 (.38) .300 (7.62) bsc (note 7) .300 (7.62) .390 (9.91) .367 (9.32) .387 (9.83) .240 (6.10) .260 (6.60) .125 (3.18) .145 (3.68) .057 (1.45) .068 (1.73) .120 (3.05) .140 (3.56) .015 (.38) minimum .048 (1.22) .053 (1.35) .100 (2.54) bsc .014 (.36) .022 (.56) -e- pin 1 sea ting plane -d- -t - p08c dip-8c pi-3933-100504 d s .004 (.10) t e d s .010 (.25) m (note 6) .137 (3.48) minimum
rev. a 09/12 23 tny284-290 www.powerint.com pi-4526-0401 10 d07c 3.90 (0.154) bsc notes: 1. jedec reference: ms-012. 2. package outline exclusive of mold flash and metal burr . 3. package outline inclusive of plating thickness. 4. datums a and b to be determined at datum plane h. 5. controlling dimensions are in millimeters. inch dimensions are shown in parenthesis. angles in degrees. 0.20 (0.008) c 2x 1 4 5 8 2 6.00 (0.236) bsc d 4 a 4.90 (0.193) bsc 2 0.10 (0.004) c 2x d 0.10 (0.004) c 2x a-b 1.27 (0.050) bsc 7x 0.31 - 0.51 (0.012 - 0.020) 0.25 (0.010) m c a-b d 0.25 (0.010) 0.10 (0.004) (0.049 - 0.065) 1.25 - 1.65 1.75 (0.069) 1.35 (0.053) 0.10 (0.004) c 7x c h o 1.27 (0.050) 0.40 (0.016) gauge plane 0 - 8 1.04 (0.041) ref 0.25 (0.010) bsc sea ting plane 0.25 (0.010) 0.17 (0.007) det ail a det ail a c sea ting plane pin 1 id b 4 + + + 4.90 (0.193) 1.27 (0.050) 0.60 (0.024) 2.00 (0.079) reference solder pad dimensions + so-8c (d package)
rev. a 09/12 24 tny284-290 www.powerint.com side view end view 11 2 7 7 pi-5748a-100311 notes: 1. dimensioning and tolerancing per asme y14.5m-1994. 2. dimensions noted are determined at the outermost extremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs, and interlead flash, but including any mismatch between the top and bottom of the plastic body. maximum mold protrusion is 0.007 [0.18] per side. 3. dimensions noted are inclusive of plating thickness. 4. does not include interlead flash or protrusions. 5. controlling dimensions in inches [mm]. 6. datums a and b to be determined at datum h. 7. exposed pad is nominally located at the centerline of datums a and b. ?max? dimensions noted include both size and positional tolerances. esop-12b (k package) b c c h top view bottom view pin #1 i.d. (laser marked) 0.023 [0.58] 0.018 [0.46] 0.006 [0.15] 0.000 [0.00] 0.098 [2.49] 0.086 [2.18] 0.092 [2.34] 0.086 [2.18] 0.032 [0.80] 0.029 [0.72] seating plane detail a seating plane to package bottom standoff 0.034 [0.85] 0.026 [0.65] 0.049 [1.23] 0.046 [1.16] 3 4 0.460 [11.68] 0.400 [10.16] 0.070 [1.78] 0.306 [7.77] ref. 2 0.350 [8.89] 0.010 [0.25] ref. gauge plane seating plane 0.055 [1.40] ref. 0.010 [0.25] 0.059 [1.50] ref, typ 0.225 [5.72] max. 0.019 [0.48] ref. 0.022 [0.56] ref. 0.020 [0.51] ref. 0.028 [0.71] ref. 0.325 [8.26] max. 0.356 [9.04] ref. 0.059 [1.50] ref, typ 0.120 [3.05] ref 0.010 (0.25) m c a b 11 0.016 [0.41] 0.011 [0.28] 3 detail a (scale = 9x) 0.008 [0.20] c 2x, 5/6 lead tips 0.004 [0.10] c 0.004 [0.10] c a 2x 0.004 [0.10] c b 0 - 8 1 2 3 4 6 6 1 7 12 2x 0.217 [5.51] 0.321 [8.15] 0.429 [10.90] 0.028 [0.71] 0.067 [1.70] land pattern dimensions 11 12 10 9 8 7 2 1 3 4 6
rev. a 09/12 25 tny284-290 www.powerint.com part ordering information ? tinyswitch product family ? series number ? package identifer p plastic dip-8c d so-8c k esop-12b ? lead finish g rohs compliant and halogen free ? tape & reel and other options blank standard confguration tl tape & reel, 1000 pcs min./mult. tny 288 p g - tl
for the latest updates, visit our website: www.powerint.com power integrations reserves the right to make changes to its products at any time to improve reliability or manufacturability. power integrations does not assume any liability arising from the use of any device or circuit described herein. power integrations makes no warranty herein and specifically disclaims all warranties including, without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement of third party rights. patent information the products and applications illustrated herein (including transformer construction and circuits external to the products) may be covered by one or more u.s. and foreign patents, or potentially by pending u.s. and foreign patent applications assigned to power integrations. a complete list of power integrations patents may be found at www.powerint.com. power integrations grants its customers a license under certain patent rights as set forth at http://www.powerint.com/ip.htm. life support policy power integrations products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of power integrations. as used herein: 1. a life support device or system is one which, (i) is intended for surgical implant into the body, or (ii) supports or sustains life, and (iii) whose failure to perform, when properly used in accordance with instructions for use, can be reasonably expected to result in signifcant injury or death to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. the pi logo, topswitch, tinyswitch, linkswitch, lytswitch, dpa-switch, peakswitch, capzero, senzero, linkzero, hiperpfs, hipertfs, hiperlcs, qspeed, ecosmart, clampless, e-shield, filterfuse, stakfet, pi expert and pi facts are trademarks of power integrations, inc. other trademarks are property of their respective companies. ?2012, power integrations, inc. power integrations worldwide sales support locations world headquarters 5245 hellyer avenue san jose, ca 95138, usa. main: +1-408-414-9200 customer service: phone: +1-408-414-9665 fax: +1-408-414-9765 e-mail: usasales@powerint.com china (shanghai) rm 1601/1610, tower 1, kerry everbright city no. 218 tianmu road west, shanghai, p.r.c. 200070 phone: +86-21-6354-6323 fax: +86-21-6354-6325 e-mail: chinasales@powerint.com china (shenzhen) 3rd floor, block a, zhongtou international business center, no. 1061, xiang mei rd, futian district, shenzhen, china, 518040 phone: +86-755-8379-3243 fax: +86-755-8379-5828 e-mail: chinasales@powerint.com germany lindwurmstrasse 114 80337 munich germany phone: +49-895-527-39110 fax: +49-895-527-39200 e-mail: eurosales@powerint.com india #1, 14th main road vasanthanagar bangalore-560052 india phone: +91-80-4113-8020 fax: +91-80-4113-8023 e-mail: indiasales@powerint.com italy via milanese 20, 3rd. fl. 20099 sesto san giovanni (mi) italy phone: +39-024-550-8701 fax: +39-028-928-6009 e-mail: eurosales@powerint.com japan kosei dai-3 bldg. 2-12-11, shin-yokomana, kohoku-ku yokohama-shi kanagwan 222-0033 japan phone: +81-45-471-1021 fax: +81-45-471-3717 e-mail: japansales@powerint.com korea rm 602, 6fl korea city air terminal b/d, 159-6 samsung-dong, kangnam-gu, seoul, 135-728, korea phone: +82-2-2016-6610 fax: +82-2-2016-6630 e-mail: koreasales@powerint.com singapore 51 newton road #15-08/10 goldhill plaza singapore, 308900 phone: +65-6358-2160 fax: +65-6358-2015 e-mail: singaporesales@powerint.com taiwan 5f, no. 318, nei hu rd., sec. 1 nei hu dist. taipei, taiwan 114, r.o.c. phone: +886-2-2659-4570 fax: +886-2-2659-4550 e-mail: taiwansales@powerint.com europe hq 1st floor, st. jamess house east street, farnham surrey gu9 7tj united kingdom phone: +44 (0) 1252-730-141 fax: +44 (0) 1252-727-689 e-mail: eurosales@powerint.com applications hotline world wide +1-408-414-9660 applications fax world wide +1-408-414-9760 revision notes date a code a data sheet. 09/12

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